As chip capacity continues to increase significantly, the use of field programmable gate arrays (FPGAs) is quickly replacing the use of application specific integrated circuits (ASICs). An ASIC is a specialized integrated circuit that is designed for a particular application and can be implemented as a specialized processor-based system. FPGA is a programmable logic device (PLD) that has an extremely high density of electronic gates as compared to an ASIC. This high gate density allows a highly flexible implementation of processor-based systems and has contributed immensely to the popularity of FPGA devices. Notably, FPGAs can be designed using a variety of architectures that can include hard and soft processor elements, user configurable input/output blocks (IOBs), and programmable logic blocks having configurable interconnects and switching capability.
The advancement of computer chip technology has also resulted in the development of embedded processors and controllers and even embedded networks having multiple linked devices. An embedded processor or controller can be a microprocessor or microcontroller circuitry that has been integrated into an electronic device as opposed to being built as a standalone module or “plugin card.” Advancement of FPGA technology has led to the development of FPGA-based system-on-chip (SoC) and network-on-chip (NoC) including FPGA-based embedded processor SoCs. A SoC is a fully functional product having its electronic circuitry contained on a single chip. While a microprocessor chip requires ancillary hardware electronic components to process instructions, SoC would include all required ancillary electronics. As platform architectural forms, SoC and NoC are nominally understood to include at least one processor-element. An obvious conceptual extension is instancing of multiple processor elements coupled to each other via a bus (SoC) or network (NoC). A simple example is a cellular telephone SoC that includes a microprocessor, encoder, decoder, digital signal processor (DSP), RAM and ROM, (i.e., two processing elements). In this context, processing elements are not restricted to microprocessor, but may include RISC, DSP, Micro-Controller, and cyclostatic processing engines or other processing elements. Furthermore, processing elements in this context should also be understood to include something more than just a mere look-up table (LUT).
In order for device manufacturers to develop FPGA-based SoCs or FPGA-based embedded processor SoCs, such device manufacturers acquire intellectual property rights for system components and/or related technologies that are utilized to create the FPGA-based SoCs. These system components and/or technologies are called cores or Intellectual Property (IP) cores. An electronic file containing system component information can typically be used to represent the core. A device manufacturer will generally acquire several cores that are integrated to fabricate the SoC. More generically, the IP cores can form one or more of the processing modules in an FPGA-based SoCs. The processing modules can either be hardware or software based.
Platform/Embedded-System design by definition involves system-level integration of processors with Intellectual Property (IP) Core components. Specific classes of processors that might be employed in such systems include RISCs, DSPs, CISCs, and micro-Controllers. Platform architectural paradigms that might be employed include System-on-Chip (SoC), Network-on-Chip (NoC), and Multi-Processor Systems-on-Chip (MP SoC). The IP Cores that might be employed in such systems are typically of a specialized nature, and take advantage of available hardware-level concurrency so as to achieve highest performance.
Hardware stacks constitute a basic and ubiquitous element often used in FPGA-based designs. Further, they can be advantageously employed in connection with FPGA-based SoCs or FPGA-based embedded processor SoCs. Hardware stacks may be employed in connection with state management in multi-threaded Super-Scalar and Very Long Instruction Word (VLIW)-style processor architectures. Processing threads thus derived may be generated within context of multi-tasking or quasi-concurrent data-flow block processing. The most common implementation is a pointer-based stack. That is, all stack elements are stored in memory, either on-chip or off-chip, with a stack pointer pointing to the top of the stack, the first element to be popped. Each stack element has a data component and a pointer, pointing to the memory address of the next stack element. This linked list implementation is efficient in terms of using only memory and being relatively energy-efficient.
Other implementations of a hardware stack use shift registers as a stack. Since every element must be shifted for every push or pop operation, this implementation engenders relatively high power consumption. Some implementations of a stack use a shift register for the first N elements where N is small and a pointer-based stack in memory is used for the backend storage of the stack. One implementation of a pointer-based stack discussed in U.S. Pat. No. 6,848,044 to Eisen et al. allows for recovering pointers to stack elements by comparing pointer addresses until the desired stack element is found. This is useful in instruction flushes.
Stack-based processors employ a stack where the last two elements placed on the stack, (i.e., stack ‘TOP’), are mapped to a special purpose register set as inputs to an arithmetic logic unit (ALU). In this configuration it is useful for at least the first two elements to be placed in their own registers and not as part of a larger memory. In this case a shift-register style stack is used for at least the first two elements. Notwithstanding the existing stack architectures known, hardware stacks are not generally known in the context of FPGAs.